FLIP FLOP

Flip Flops stores binary value 1 or binary value 0. Flip Flops are used as storage elements in digital circuits. It is a bistable gate that is interconnected with similar type of Electronics circuits to form logic gates in digital integrated circuits, such as memory chips and microcontrollers like 8051, 8052. A flip-flop keeps its state say on or off continuously till it receives an input pulse, which is called a trigger which makes it change its state. Once the circuit changes state it continuously remains in that state whether it is ON or OFF until it gets another trigger or an input pulse.

RS Flip-Flop

An RS Flip Flop is an combination of logic gates that gives a stable output even after the inputs are turned off. This Latch or a simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 and 1. The reset input makes it reverse 1 and 0 .Once the outputs come, the electrics of the circuit is maintained until S or R go high, or we turn off the power of our circuit.

D-Flip-Flop

We can set or reset a D flip Flop by applying a high level to its set or reset input. The data on D input is transferred to output on rising edge of clock pulse. The edge-triggered D flip-flop can be lucidly made from RS Flip Flop. When the clock input is at logic 0 which means outputs can change state, the output always takes on the state of the D input at the time of the clock edge. This is not the case with the RS and JK flip-flops. The RS master part would continuously change states to match the input signals provided the clock line is at a logic 1, and the other output would show latest input received ,an active signal.The JK master section would receive and hold an input to tell it to change state, and never change that state until the next cycle of the clock. This type of behavior is impossible with a D flip-flop.

JK Flip Flop

J-K Flip Flop is more versatile than a D type Flip Flop. Logic circuit of J-K Flip Flop is shown above. Integrated Circuit Type D4027 has two identical independent J-K Flip Flops in one package. Changes in Flip Flop Output state are synchronous with positive going transition of clock pulse.